How To Make A PIC Programmer From Scratch, The Newbie Way

So I had a flu… Wouldn’t go out.. Couldn’t anyway… And decided to learn CadSoft Eagle.

I opened a thread about Microcontrollers recently on the great Electro-tech-online.com , and I wanted to build a PIC Programmer … I’ll eventually buy  a “real” one (PICKit 2 or something), I just wanted to lose my PCB virginity with this project.

Anyway, I wanted something simple, so I exluded de facto clones with microcontrollers which have to be programmed in the first place inside them  (The ones I found had a PIC18 inside, like PICKit2 clones).

Anyway… Eagle thingy..

The project I chose is a JDM Serial PIC Programmer… (JDM stands for Jens Dyekjaer Madsen) which I found here :

http://webspace.webring.com/people/jl/leon_heller/pic.html

And which the author found here :

http://www.jdm.homepage.dk/newpics.htm

He substituted the 25 pin connector with a 9 pin connector ( DB25 – DB9 … RS-232) .. I like the DB9 more.

I worked with the schematic from the original page. Have in mind though that pins like TxD (2) or GND (7) refer to the DB25 Pinout, while I’m going to do a DB9 version.

To get the corresponding pins in a DB9, you can search for something like « RS232 pinout » or « DB9 pinout » or something like that..

Or you can find it directly here :  http://pinouts.ru/SerialPorts/Serial9_pinout.shtml

Anyway … Here are schematics I did…

Notice how angles are « rounded », it’s called « Mitering », there’s a button for it on the left panel.

Here’s ultimately the « Board », revision 4…

I drew a rectangle on the whole surface on vRestrict layer, I didn’t want any Vias in there. I’m a beginner, so I didn’t want to  bother with that just  yet.

I drew two small rectangles under the PIC microcontroller, on two layers tRestrict and bRestrict, they coincide, so you only see one.

I didn’t want any routing under the PIC, because I thought it would be better (Less heat influencing its functionning, and I wanted to diminish the influence of a field that would be created by the the current in a hypothetical route. I know, I know.. Actually, I don’t. I asked questions about this on the forum, if I’m overthinking or not.)

I had a problem as shown in the image, where these rectangles crossed over the pads, and it showed errors when I hit DRC (Design Rules Check), here’s a zoom in:

Note how tiny it is, the pads crossed over the restricted surface, and this provoked an error. Amazing software.

I couldn’t draw accurate enough rectangles to include the whole chip, or “just” the chip. i.e : It was either too small, or a little bit too big.. So I increased the Grid resolution by chosing 5 mils in « Size ». I could draw  my rectangles with more precision.

I managed to have a single sided board before (drawing a rectangle in the tRestrict Layer over the whole board), but NOT with that disposition, and it was a LOT of gymnastic. This one is very symmetrical as you can see here :

Here it is with Dimension, Top, Pads, tNames, tPlaces…

It’s a relatively small board  1.8’’ by 2.135’’.

Here’s an image with all layers..

I asked some questions about design faults on the forum mentionned, if you don’t know it, well you should check it out.

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